testbench.v

// Testbench for PicoRV32 Arty A7-100T system

`timescale 1ns/1ps

module tb_picorv32_arty;

    reg clk;
    reg rst_n;
    wire [3:0] led;
    wire [2:0] led0_rgb, led1_rgb, led2_rgb, led3_rgb;
    reg [3:0] sw;
    reg [3:0] btn;
    wire uart_txd_in;
    reg uart_rxd_out;
    
    // Clock generation (100MHz)
    initial begin
        clk = 0;
        forever #5 clk = ~clk;  // 100MHz = 10ns period
    end
    
    // Reset generation
    initial begin
        rst_n = 0;
        sw = 4'b0000;
        btn = 4'b0000;
        uart_rxd_out = 1'b1;
        #200;
        rst_n = 1;
        
        // Test different switch modes
        #5000000;  // Wait 5ms
        sw = 4'b0001;  // Mode 1
        #5000000;
        sw = 4'b0010;  // Mode 2
        #5000000;
        sw = 4'b0011;  // Mode 3
        btn = 4'b0101;  // Press some buttons
        #5000000;
        sw = 4'b0000;  // Back to mode 0
    end
    
    // Instantiate DUT
    picorv32_arty_top dut (
        .clk(clk),
        .rst_n(rst_n),
        .led(led),
        .led0_rgb(led0_rgb),
        .led1_rgb(led1_rgb),
        .led2_rgb(led2_rgb),
        .led3_rgb(led3_rgb),
        .sw(sw),
        .btn(btn),
        .uart_txd_in(uart_txd_in),
        .uart_rxd_out(uart_rxd_out)
    );
    
    // Monitor LED changes
    always @(led) begin
        $display("Time %0t: LEDs = 0x%h", $time, led);
    end
    
    // Monitor RGB LED changes
    always @(led0_rgb or led1_rgb or led2_rgb or led3_rgb) begin
        $display("Time %0t: RGB LEDs = 0:%h 1:%h 2:%h 3:%h", 
                 $time, led0_rgb, led1_rgb, led2_rgb, led3_rgb);
    end
    
    // Simulation control
    initial begin
        $dumpfile("picorv32_arty.vcd");
        $dumpvars(0, tb_picorv32_arty);
        
        // Run simulation for 30ms
        #30000000;
        
        $display("Simulation completed successfully");
        $finish;
    end
    
    // Timeout watchdog
    initial begin
        #50000000;  // 50ms timeout
        $display("ERROR: Simulation timeout!");
        $finish;
    end

endmodule