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@OR5-LABS

OR5 LABS

Open RISC V labs

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  1. MIST-ES MIST-ES Public

    Area-optimized, fully verified RV32IMC multi-cycle RISC-V core for embedded & FPGA.

    C 2 2

  2. 3-SIPP-ESR 3-SIPP-ESR Public

    A verified compact 3-stage RV32IMAC RISC-V core with FreeRTOS and Security support

    SystemVerilog 2 2

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Showing 2 of 2 repositories
  • MIST-ES Public

    Area-optimized, fully verified RV32IMC multi-cycle RISC-V core for embedded & FPGA.

    OR5-LABS/MIST-ES's past year of commit activity
    C 2 MIT 2 0 0 Updated Oct 22, 2026
  • 3-SIPP-ESR Public

    A verified compact 3-stage RV32IMAC RISC-V core with FreeRTOS and Security support

    OR5-LABS/3-SIPP-ESR's past year of commit activity
    SystemVerilog 2 MIT 2 0 0 Updated Oct 21, 2026

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