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perf(pt): fused Triton zonal scatter for the GIE head (DP_GIE_SCATTER_INFER) - #6072
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Check name Status Explanation Description Check Check skipped - CodeRabbit’s high-level summary is enabled. Title check The title clearly and concisely describes the main change: adding a fused Triton zonal scatter for the GIE head. Linked Issues check Check skipped because no linked issues were found for this pull request. Out of Scope Changes check Check skipped because no linked issues were found for this pull request.
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Actionable comments posted: 2
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Review comments at @deepmd/pt_expt/kernels/triton/sezm/gie_scatter.py:
- Line 107: Update _forward_impl and _backward_impl to route non-power-of-two
channel dimensions to the reference implementation before Triton dispatch, and
apply the same guard when assigning _triton_scatter in
GeometricInitialEmbedding; ensure the public gie_zonal_scatter entrypoint is
protected independently of the embedding guard.
Review comments at @deepmd/pt/model/descriptor/sezm_nn/embedding.py:
- Around line 329-334: Update the fused Triton dispatch condition in
embedding.py, lines 329–334, to require evaluation mode and the supported
CUDA/force-fused-scatter target; keep training on the existing non-fused path.
The missing autograd formula at gie_scatter.py, lines 412–414, requires no
direct change for this fix.
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📒 Files selected for processing (4)
deepmd/pt/model/descriptor/sezm_nn/embedding.pydeepmd/pt_expt/kernels/triton/sezm/gie_scatter.pydeepmd/pt_expt/kernels/utils.pysource/tests/pt/model/test_descriptor_sezm_triton.py
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@OutisLi @wanghan-iapcm @njzjz requesting a review, please. Following the 2026-10-13 discussion we validated the combined stack of our six performance PRs (#6056, #6057, #6060, #6070, #6071, #6072) with a multi-scale gate: diamond + bcc-Cu at ~500 / ~2000 / ~4400 atoms, three columns (pure torch.compile with all custom kernels off / current master / our changes on). All accuracy cells sit within 2.2x the pure baseline's own run-to-run band (criterion: 3x), and no tested atom count regresses in time or memory — full numbers in the PR descriptions. Suggested review order for the six: #6056 -> #6057 -> #6060 (small and self-contained) -> #6070 -> #6071 -> #6072. |
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I reviewed the exact head. The existing findings at gie_scatter.py:107 and embedding.py:329 remain correctness blockers: arbitrary channel counts can fail Triton compilation, and the fused backward can be selected during training without the required higher-order autograd support. Please address those threads, then rerun the failing pre-commit and documentation checks.
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I reviewed the exact head. The existing findings at gie_scatter.py:107 and embedding.py:329 remain correctness blockers: arbitrary channel counts can fail Triton compilation, and the fused backward can be selected during training without the required higher-order autograd support. Please address those threads, then rerun the failing pre-commit and documentation checks.
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Reviewed only 288e49c → 4f42e82 and the existing review threads. The training gate is now present. The padded channel extent fixes the earlier Triton range constraint, but introduces the out-of-bounds backward reads described inline; the prior resolved channel thread did not identify this omission in the new fix.
Validation: exact-source inspection plus arithmetic bounds and NumPy reduction checks, not CUDA/Triton execution. For the added test shape (777, 3, 40), the final radial load accesses 24 floats beyond the contiguous allocation. Current Actions still require approval, so they provide no execution evidence for this head.
Agent: dot
| offs_c = tl.arange(0, BC) | ||
| cmask = offs_c < C |
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[P2] Mask the padded channels in backward's radial loads
Expanding offs_c to BC makes channels C..BC-1 real load lanes, but the three rd0/rd1/rd2 loads at lines 245–252 still use only mask_e[:, None]. For the newly added case C=40, BC=64 with contiguous radial.shape == (777, 3, 40), the last edge's slot-2 load reads float offsets 93,240–93,263 from an allocation containing only 93,240 floats. The forward loads and gradient stores are masked, but those masks do not protect these backward reads.
The padded values also enter tl.sum(g*rd, 2) at lines 254–256; zeroing padded g cannot prevent NaN/Inf data from contaminating valid zonal gradients. Please apply mask_e[:, None] & cmask[None, :] with other=0.0 to all three radial loads, and validate the non-power-of-two backward path with bounds/sanitizer coverage. This is an address-arithmetic/source finding, not a claimed CUDA crash reproduction.
Agent: dot
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Thank you for the review — both findings are real and addressed in 4f42e82:
Validation at the new head: the full |
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Reviewed e26dbcc5c2700a601daf3f0cbf7c9b88a45acd33. Avoiding the materialized per-edge GIE message is a meaningful optimization for the Triton path, but the current backward memory access and integration need changes before merge.
Required changes
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Fix the remaining out-of-bounds radial loads in backward.
The existing padded-channel review thread is still valid at this head; I am confirming it rather than opening a duplicate inline thread. The three radial loads mask invalid edges but not padded channels. WithC=40, BC=64, a contiguousradial[17, 3, 40]contains 2040 floats, but the last slot load reaches offset 2063.A small CPU-interpreter replay of the exact kernel used safely allocated backing storage beyond the logical radial tensor, with all logical inputs finite and NaN sentinels outside that tensor. It produced seven NaNs in valid zonal-gradient entries; the 32-channel control remained finite and matched the reference. Zero padded upstream gradients cannot protect the reduction because
0 * NaNis still NaN. This is an arithmetic/addressing reproduction, not a claimed GPU crash.Apply the joint edge/channel mask, with zero masked values, consistently to every affected radial load. Keep that validity condition shared so the three degree-group copies cannot diverge.
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Remove the new public environment switch and integrate with the existing levels.
DP_GIE_SCATTER_INFERshould not be added to the public interface. Do not replace it with another micro-switch or introduce a new acceleration level. First assess whether the kernel can satisfy the existing level-1 universal-kernel contract and implement it there if it can; a new fused kernel is not automatically level 2. Only if hardware/shape-dependent table selection is actually needed should it use level 2, with freeze-time autotuning/registration and evidence from hardware available to the author included in this PR. Precomputed parameters for inaccessible GPUs are not required. -
Unify the shared Python control flow instead of adding a parallel copy.
The new Triton branch duplicates the CUDA branch's message eligibility conditions, destination-CSR acquisition and input preparation. Share these decisions and select the backend implementation at a clear boundary. The CUDA and Triton kernels themselves have legitimate backend differences, including where normalization is applied; preserve those differences without duplicating the surrounding forward path. Retain the training, source-gate and native-spin-message exclusions and the intended runtime/trace-target policy. -
Make the claimed strided-input coverage real and keep tests small.
The test'sradial.clone()materializes its sliced input into contiguous storage. In the CPU check, the purported view's stride changed from(160, 40, 1)to(120, 40, 1). Consequently, the contiguous and view cases both feed contiguous radial inputs to the operator.Copy independent parent tensors before slicing, preserve the slice at the actual operator boundary, and assert its stride/non-contiguity before the call. Use small deterministic edge sets to cover padded channels, a partial backward edge tile and isolated destination nodes. For module dispatch, isolate the existing backend gates and assert which callable is selected; output equality alone can pass when both states use the existing path. Keep production-scale performance checks separate from ordinary CI rather than adding more large GPU regressions.
Verification and limits
The earlier missing training-mode gate and original non-power-of-two arange limitation have been addressed; they are not being raised again. The remaining backward load masks are a separate omission in the padded-channel implementation.
CPU interpreter checks covered the exact forward/backward kernels for 32 and 40 channels, including the guarded-sentinel reproduction above, and the stride probe confirmed the test gap. Ruff and diff whitespace checks passed. CUDA was hidden and remained uninitialized. GPU compilation, performance, and the author's reported memory reduction were not independently validated in this review.
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Thank you — the guarded-sentinel reproduction and the stride probe were both decisive. All four items are addressed in dc806f3:
Validation at the new head: the full |
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Reviewed the e26dbcc → dc806f3 delta and the affected constructor/reference-path integration.
The earlier padded radial-load defect is addressed: all three loads now share the joint edge/channel mask with zero fill. The updated regression keeps the parent-backed strided operand at the operator boundary. An exact-kernel AST/NumPy replay passed 25 current-head forward/backward cases; the old C=40 control reproduced 24 logical out-of-bounds reads and seven nonfinite zonal gradients, while the new source had neither. This is host modeling of the actual kernel source, not a Triton/CUDA execution. The author's reported 43-pass GPU run is separate evidence.
Two new integration issues are inline: an optional-Triton import now breaks ordinary level-1 construction without Triton, and the shared dispatch builds destination CSR even when the reference path is selected. Both were checked against the old/new exact source with control-flow/import doubles; no full PyTorch model or performance timing ran locally.
Current head has a merge conflict and only the labeler/triage check; no test workflow execution is present on this SHA. The current-head CodeRabbit summary was checked before posting and has no equivalent finding.
Agent: dot
| if triton_infer_level() >= 1 and self.dtype is torch.float32 and self.lmax == 3: | ||
| from deepmd.pt_expt.kernels.triton.sezm.gie_scatter import ( | ||
| GIE_SCATTER_TRITON_AVAILABLE, | ||
| gie_zonal_scatter, | ||
| ) |
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[P2] Preserve the fallback when Triton is not installed
Routing this import through the existing DP_TRITON_INFER level now makes construction of an fp32, lmax=3 embedding import gie_scatter whenever the level is 1/2/3, including CPU/no-Triton environments. That module unconditionally executes import triton at line 33, so construction raises ModuleNotFoundError before GIE_SCATTER_TRITON_AVAILABLE can keep the reference path. Other SeZM Triton modules handle ImportError and leave availability false.
With DP_CUDA_INFER=0, DP_TRITON_INFER=1, and Triton unavailable, an exact-source constructor/import probe initializes the previous head with _triton_scatter=None; this head raises No module named 'triton'. This used tensor/import doubles, not a full PyTorch model test. Please guard the optional import or make the module safely importable without Triton, and cover level-1 construction in that environment.
Agent: dot
| cached_edge_csr, | ||
| ) | ||
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| order, row_ptr = cached_edge_csr(edge_cache, "dst", n_nodes) |
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[P2] Check backend eligibility before building destination CSR
The shared branch now calls cached_edge_csr before either backend is selected. The normal edge builder initializes csr_cache={}, so default eager inference with all accelerators off, and the ordinary training/reference path, now execute a stable destination argsort plus count/row-pointer allocation before falling through to the unchanged index_add_ implementation. The default SO2 reference consumers do not need this destination CSR either; their CSR consumers are accelerator-gated.
An exact old/new control-flow probe with a fresh cache changes from zero CSR calls/sorts to one call/sort on these fallback paths. A prefilled cache avoids rebuilding, and later accelerated consumers can reuse it; no full-model timing is claimed. Keep the common dispatch structure, but acquire CSR only after confirming that the CUDA path or the inference-only Triton path will actually run.
Agent: dot
for more information, see https://pre-commit.ci
…catter boundary for the GIE head - The backward's three radial loads now carry the shared joint edge/channel mask: a padded channel lane reading past the tensor dragged NaN into valid zonal-gradient entries (0 * NaN is NaN). A NaN-sentinel regression test (radial as a slice of a NaN-filled parent, leaf on the parent so the backward walks the padding) fails on the old kernel and passes on the fixed one. - DP_GIE_SCATTER_INFER is removed; the operator rides the level-1 universal-kernel contract (no tunable configuration, strictly removes the message round-trip). - One eligibility block and one destination-CSR acquisition now serve both fused backends; only the backend call differs at the boundary. - The strided-input coverage is real now: the view case reaches the operator as a parent-backed slice with an asserted non-contiguous stride; small deterministic topologies cover isolated nodes, short segments and a BLOCK_E boundary; module dispatch asserts which path ran via a counting operator.
…o a fused backend
dc806f3 to
7103523
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Both integration findings addressed in 7103523 (the branch is also rebased on current master, resolving the merge conflict you noted; the #6045 merge had removed the source-gate mechanism this dispatch previously checked, so the eligibility set was aligned with master's semantics):
Your exact-kernel replay confirming the masked-load fix (24 logical out-of-bounds reads and 7 nonfinite gradients on the old head, neither on the new one) is much appreciated — that, plus our GPU sentinel test that fails on the old kernel and passes on the new one, closes the loop from both sides. Validation at the new head: the full |
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Scoped fix verification at exact head 71035233564c9338c746d7994114df18426eea56, rebased onto 668b60cc2a9559f79abb9c33acd959833376344f.
Both P2 issues in my preceding review are fixed: the optional Triton import is guarded, and destination CSR is acquired only after selecting a fused backend. Exact-source replay of the rebased predecessor raises ModuleNotFoundError without Triton; current construction retains the reference path. Ordinary fallback/training now performs zero CSR lookups/sorts, while eligible fused calls acquire CSR once, reuse a prefilled cache and retain CUDA precedence. Ninety-six dispatch cases and 24 constructor cases with host doubles pass.
I also checked the necessary rebase integration: removal of edge_src_gate agrees with current master; the leave-one-out gate still enters the cutoff envelope, the envelope still weights radial features before GIE, and the readout node gate remains intact. The kernel and Triton-test files are byte-identical to the previously reviewed padded-load fix, so that investigation was not repeated. No new actionable defect was found in this bounded delta.
These checks do not execute Torch/Triton or GPU kernels. The 43 passes and one pre-existing skip are author-reported. The merge conflict is gone; seven current-head workflows still require approval. This records the specific fixes, not overall approval or a replacement for the requested human review.
Agent: dot
What
One Triton operator replaces the reference composition of the geometric initial embedding's message path ("broadcast the per-edge zonal coupling over each degree's radial rows, then
index_add-scatter it onto the destination nodes"):(N, D, C)node layout with a zero scalar row. The per-edge message surface —(E, D-1, C), 1.2 GB at the production shape — is never materialized, and it also stops being held until the backward has re-read it, which is where most of the peak-memory win comes from.(E, D-1)coupling and(E, lmax, C)radial) in a single pass; no gather of a materialized message gradient.index_add_addition order, so outputs sit at the usual scatter-order noise floor rather than drifting.Boundary and layout contract
Same operator boundary as the existing CUDA
zonal_scatter(DP_CUDA_INFER >= 1), serving the Triton inference stack instead. Inputs are flattened to contiguous in the traced graph before entering the op (the contract every othersezm_tritonoperator already uses). The kernel specializes on the packed contiguous row layout of thelmax = 3ladder (row groups 3/5/7); any other configuration, dtype or training keeps the reference composition, so the flag is strictly opt-in and the reference path is untouched.The flag is
DP_GIE_SCATTER_INFER, default off, read at module construction.Numbers
DPA4-Neo checkpoint, N=4096 diamond frame, RTX 5090, torch.compile inference, same tree two-state (flag off vs on):
The -1.2 GB peak drop is the removed
(E, 15, 32)message surface. At the kernel level the message build+scatter composites and the backward composite that re-read the saved message (together ~3.4 ms at this edge count) are replaced by a 0.2 ms forward and a 0.5 ms backward kernel.Correctness against the flag-off state: energy rel 7.7e-10, forces rel 1.1e-6 (the established scatter-order noise floor for this benchmark).
Tests
Operator vs reference composition (forward plus shared-cotangent gradients, contiguous and sliced-view radial inputs), CPU reference vs hand-written sequential accumulation, compiled-vs-eager (forward and gradients — this guards the custom-op launch-grid trap), and a module-level two-state check of
GeometricInitialEmbeddingwith gradients.Merge-order note
Touches
embedding.pyandkernels/utils.py, which #6071 also touches (banded Wigner storage); the hunks are disjoint and both directions rebase trivially.Summary by CodeRabbit