[leejet]

Summary

• Accelerate eligible W4A4 operations with CUTLASS mixed-input S8 × S4 GEMM, reusing the INT8 tile selection and scale epilogue without expanding the full weight tensor.
• Accelerate W4A8 with CUTLASS integer MMA and FP32 scale restoration for each 16-element group.
• Preserve existing fallback paths and HIP/MUSA implementations. Add GGML_CUDA_W4_FORCE_DP4A=1 for comparison.

Related Issue / Discussion

N/A

Additional Information

Hardware: NVIDIA GeForce RTX 4090 24 GB, NVIDIA driver 596.36.

Build: Windows, CUDA 13.4, nvcc 13.4.92, Release, CUTLASS enabled.

DiT files:

Model	Format	DiT file
Krea2 Turbo	W4A4	krea2_turbo_int4_tensorwise_mixed.safetensors
Krea2 Turbo	INT8	krea2_turbo_int8_convrot.safetensors
P-H3 Image	W4A8	p-h3-image_w4a8.safetensors
P-H3 Image	INT8	p-h3-image_int8_convrot.safetensors

Sampling throughput in it/s; higher is better. Before/after uses the same INT4 weights:

Model	Resolution	sd.cpp before	sd.cpp after	Improvement
Krea2 Turbo W4A4	512×512	2.438	10.167	+316.98%
P-H3 Image W4A8	2912×2912	0.124	0.342	+176.25%

Percentages are calculated before rounding the reported throughput values.

INT8 reference using the same inference settings:

Model	Optimized INT4	INT8
Krea2 Turbo	10.167	11.269
P-H3 Image	0.342	0.289

Configuration and measurement:

• CUDA backend, batch 1, CFG 1, Euler, seed 42, CPU offloading enabled.
• Automatic flash attention selected CUDA MMA.
• Eight steps per run. Exclude steps 1–2 from the throughput calculation; all eight steps execute.
• Krea2 uses the discrete scheduler, Qwen3-VL-4B-Instruct-Q4_K_M.gguf, and wan_2.1_vae.safetensors.
• P-H3 uses --sigmas p-h3-image --rng cpu, qwen3vl_4b_bf16.safetensors, p-h3-image_text_connector.safetensors, and p-h3-image_vae_bf16.safetensors.

Checklist

• I have read and confirmed this PR follows the contribution guidelines.

Summary by CodeRabbit

• Performance
  • Improved CUDA execution for packed INT4 operations on supported NVIDIA GPUs, with optimized paths for eligible workloads.
  • Other shapes and configurations continue to use existing execution paths.
• Documentation
  • Clarified which CUDA execution paths are used for packed INT4 operations and documented an option for comparing performance.

[coderabbitai]

Walkthrough

The CUDA W4 backend now supports CUTLASS execution paths for eligible operations. Packed-W4 I8 GEMM handles W4A4 cases, and a new MMA kernel handles W4A8. Other cases retain existing paths.

Changes: CUDA packed W4 execution

Layer / File(s)	Summary
Packed-W4 I8 GEMM support src/core/cuda/i8_gemm.h, src/core/cuda/i8_gemm.cu	The I8 GEMM API accepts an optional packed_w4 flag. Packed-W4 plans select the corresponding weight type, alignment, multiplication mode, and tile configuration.
W4A8 MMA kernel and build support src/core/cuda/w4_mma.h, src/core/cuda/CMakeLists.txt	The W4A8 kernel uses CUTLASS int8 MMA on SM80+ and a scalar fallback below SM80. CMake applies CUTLASS compile settings to the generated W4 CUDA source.
W4 plan and runtime dispatch src/core/cuda/w4.cu, docs/int8_convrot.md	The W4 plan selects eligible MMA execution, prepares optional W4A4 GEMM workspace, and retains fallback paths. The documentation describes the CUDA paths and comparison variable.

Estimated code review effort: 3 (Moderate) | ~25 minutes

Change: Feature

Sequence Diagram(s)

sequenceDiagram
  participant W4Backend
  participant I8GEMM
  participant W4MMKernel
  W4Backend->>I8GEMM: Prepare eligible W4A4 without bias
  W4Backend->>W4Backend: Store execution plan and workspace
  alt Prepared GEMM is available
    W4Backend->>I8GEMM: Execute W4A4 GEMM
  else MMA selected without prepared GEMM
    W4Backend->>W4MMKernel: Launch W4 MMA kernel
  end

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Possibly related PRs

• leejet/stable-diffusion.cpp#2253: Adds CUTLASS configuration and generated CUDA wrapper sources used by this change.
• leejet/stable-diffusion.cpp#2276: Adds the packed W4 convrot operator and the existing W4A4 DP4A and W4A8 kernels extended here.
• leejet/stable-diffusion.cpp#2235: Adds the I8 GEMM API that this change extends for packed-W4 weights.

Merge Risk: Minimal · up to a85ad

No concrete issue remains that should block merging after normal build and numerical checks.

Pre-merge checks: 4 · 1

Failed checks: 1 warning

Check name	Status	Explanation	Resolution
Docstring Coverage		Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff with cyclomatic complexity of at least 2. Documentat…	Write docstrings for the functions missing them to satisfy the coverage threshold.

Passed checks: 4 passed

Check name	Status	Explanation
Title check		The title clearly and concisely describes the main change: accelerating packed INT4 CUDA inference with CUTLASS.
Description check		The description includes all required sections, explains the implementation and purpose, records related discussion status, provides detailed hardware and benchmark information, and confirms the contr…
Linked Issues check		Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check		Check skipped because no linked issues were found for this pull request.

Full details: Description check

Explanation

The description includes all required sections, explains the implementation and purpose, records related discussion status, provides detailed hardware and benchmark information, and confirms the contribution checklist.

Full details: Docstring Coverage

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Resolution

Write docstrings for the functions missing them to satisfy the coverage threshold.

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Reviewing files that changed from the base of the PR and between 7952693 and a85ad86.

Files selected for processing: 6

• docs/int8_convrot.md
• src/core/cuda/CMakeLists.txt
• src/core/cuda/i8_gemm.cu
• src/core/cuda/i8_gemm.h
• src/core/cuda/w4.cu
• src/core/cuda/w4_mma.h

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