controlpath

Here are 5 public repositories matching this topic...

Ecolash / RISC-Processor

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | 𝗖𝗦𝟯𝟵𝟬𝟬𝟭 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

pipeline processor assembler vivado assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture iitkgp control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design

Updated Sep 14, 2025
Verilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

Star

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm

Updated May 28, 2024
Verilog

vipul43 / RISC_V_architecture_design

Star

designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE

datapath verilog-hdl xilinx-vivado riscv64 controlpath risc-varchitecture hennessy-and-patterson

Updated Apr 23, 2020
Verilog

ARohithReddy / multiplier

Star

Digital circuit description to perform multiplication with data_path and control_path using verilog

verilog datapath multiplier data-path verilog-code controlpath

Updated Jul 30, 2020
Verilog

nmalamas / Computer-Organization

Star

VHDL labs for Computer Organization (HRY302) at the Technical University of Crete (Spring 2024): designing a MIPS-like processor from basic building blocks, including the ALU, register file, datapath, control unit, memory and a pipelined implementation.

mips vhdl mips-assembly datapath pipelining computer-architecture xilinx-fpga xilinx-vivado processor-design controlpath

Updated Sep 25, 2026
VHDL

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