#
softcore-processor-design
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This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.
Updated
Sep 26, 2024
Verilog
Rescuing Moore’s Law via Room-Temperature Soliton Integration in Standard Silicon.
Updated
Apr 22, 2026
SystemVerilog
Build a Gardner Logic-Bridge IP core for threshold-programmable, room-temperature soliton logic in standard silicon
Updated
Oct 3, 2026
SystemVerilog
A formally verified, C programmable, custom ISA 160LUT softcore.
Updated
Sep 27, 2026
Assembly
The lightweight RISCV core.
Updated
Jul 15, 2026
SystemVerilog
PandaBuilder by Logic Solutions Bründler
Updated
Sep 12, 2026
VHDL
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