32-bit Superscalar RISC-V CPU
CPU Benchmarks Set
LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
5-stage RV32IM RISC-V CPU and FPGA SoC in SystemVerilog, featuring forwarding, hazard control, machine-mode CSR/traps, precise timer interrupts, TCM, UART, GPIO, and FreeRTOS bring-up.
Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.
Forth language port of CoreMark benchmark (https://www.eembc.org/coremark)
ArduinoCoreMark is a CPU performance benchmark for Arduino platform based on EEMBC CoreMark.
A verified compact 3-stage RV32IMAC RISC-V core with FreeRTOS and Security support
This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC
Architecture and Performance Evaluation of EEMBC::CoreMark benchmark on BOOM CPUs (Small & Large).
5-stage pipelined RV32IMC RISC-V CPU + SoC in Verilog: branch prediction, caches, ISS co-simulation, constrained-random + 100% functional coverage, riscv-formal, ECP5 FPGA timing closure
A stable version of nexus-am (created by jyy).
To associate your repository with the coremark topic, visit your repo's landing page and select "manage topics."